The present invention relates to a display apparatus comprising a display panel with display pixels arranged in matrix, and a display drive circuit for selecting the display pixels to be impressed with a gray scale voltage, or in particular to a display apparatus employing liquid crystal, organic EL or plasma and a display drive circuit therefor.
According to JP-A-6-161390 (laid open Jun. 7, 1994), a liquid crystal material is sealed between each of a plurality of pixel electrodes and a corresponding one of opposed electrodes, and the pixel electrodes are each connected with a switching transistor. A scanning signal for turning on/off the switching transistor is applied from a scanning signal supply circuit through a scanning signal line to the switching transistor. An image signal is supplied from an image signal supply circuit through an image signal line and the switching transistor to each pixel electrode. The scanning signal on an adjacent scanning signal line is supplied to the pixel electrode through an additional capacitor. Further, a compensation voltage is applied before and after the voltage level of the scanning signal for turning on the switching transistor. In other words, according to the disclosure of JP-A-6-161390, the off voltage of the scanning signal is changed during the non-overlap period of the scanning signal.
On the other hand, JP-A-11-64821 (laid open Mar. 5, 1993) discloses:
a display panel including an array substrate, an opposed substrate arranged in opposed relation to the array substrate and a light modulation layer held between the array substrate and the opposed substrate, the array substrate having a plurality of signal lines, a plurality of scanning lines and a plurality of pixel electrodes, the signal lines and the scanning lines being arranged to intersect each other, the pixel electrodes being each arranged in the neighborhood of a corresponding one of the intersections between a corresponding one of the signal lines and a corresponding one of the scanning lines through a corresponding one of a plurality of switch elements;
signal line drive means for supplying a video signal voltage to the signal lines; and
scanning line drive means for supplying the scanning lines with scanning pulses having a first voltage for turning on the switch elements and a second voltage for turning off the switch elements;
wherein a pixel electrode connected to one of the scanning lines through a switch element electrically forms a capacitor with another scanning line through a dielectric layer, and the turn-on period of the switch element of a given scanning line is not substantially in superposed relation with the turn-on period of another switch element.
Further, JP-A-10-221676 (laid open Aug. 21, 1998) discloses a plurality of V scanners connected with a plurality of gate lines arranged in rows, a plurality of H scanners connected with a plurality of signal lines arranged in columns and a plurality of pixel units arranged at the intersections, respectively, between the gate lines and the signal lines;
wherein the V scanners are divided into first V scanners connected to the odd-number gate lines, respectively, and second V scanners connected to the even-number gate lines, respectively,
wherein the nth gate line of the first V scanners is connected in series with a NAND circuit and a buffer circuit, with the unconnected input terminal of the NAND circuit being connected to the end terminal of the (n−1)th gate line of the second V scanners through an inverter circuit, while the nth gate line of the second V scanners is connected in series with a NAND circuit and a buffer circuit, with the unconnected input terminal of the NAND circuit being connected to the end terminal of the (n−1)th gate line of the first V scanners through an inverter circuit, thereby preventing the gate lines from being selected in overlapped relation, and
wherein a selective pulse is supplied to every other gate through the buffer circuits and the NAND circuits connected to the first and second V scanners so that adjacent gate pulses are not overlapped with each other.
One scanning period is set by a line pulse, and one frame period is set as the product of one scanning period and the number of drive lines. The gate pulse applies a gate line select voltage to the first line in synchronism with the trailing edge of the line pulse when the frame pulse is at high level. After that, the gate pulse is applied to subsequent lines sequentially in synchronism with the line pulse. In the case where the output of the gate driver is used for a panel configured of an additional capacitor Cadd, for example, the black display brightness of normally black liquid crystal increases, thereby sometimes making it impossible to obtain the proper contrast. This abnormal increase in display brightness is attributable to the fact that the liquid panel is configured of a Cadd. The pixel electrodes are each connected to the gate line in the preceding stage through a Cadd. When a high-level voltage is applied to the gate line in the preceding stage, the pixel electrode is changed to high-voltage side through the Cadd, resulting in a correspondingly abnormal increase in display brightness.
None of the conventional techniques described above, however, takes note of the abnormal increase in display brightness with a reduced contrast.